EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Summary of Operation Codes

Table 24.  Operation Codes for EPCQ-L Devices
Operation Operation Code 18 Address Bytes Dummy Cycles Data Bytes DCLK fMAX (MHz)
Read status register 05h 0 0 1 to infinite 19 100
Read flag status register 70h 0 0 1 to infinite 100
Read bytes 03h 4 0 1 to infinite 19 50
Read non-volatile configuration register B5h 0 0 2 100
Read device identification 9Eh or 9Fh 0 2 1 to 20 19 100
Fast read (AS x1) 0Bh 4 8 20 1 to infinite 19 100
Extended quad input fast read (AS x4) EBh 4 10 20 1 to infinite 19 100
Dual I/O fast read BBh 4 10 1 to infinite 100
Write enable 06h 0 0 0 100
Write disable 04h 0 0 0 100
Write status 01h 0 0 1 100
Write bytes 02h 4 0 1 to 256 21 100
Write non-volatile configuration register B1h 0 0 2 100
Extended quad input fast write bytes 12h 4 0 1 to 256 21 100
Extended dual input fast write bytes D2h 4 0 1 to 256 100
Erase bulk 22 C7h 4 0 0 100
Erase die 23 C4h 4 0 0 100
Erase sector D8h 4 0 0 100
Erase subsector 20h 4 0 0 100
4BYTEADDREN B7h 0 0 0 100
4BYTEADDREX E9h 0 0 0 100
18 List MSB first and LSB last.
19 The status register, data, or read device identification is read out at least once and is continuously read out until the nCS pin is driven high.
20 The default EPCQ-L dummy clocks are 8 and 10 for the fast read and extended quad input fast read operations, respectively. The Intel® Quartus® Prime Programmer configures the NVCR automatically during the JIC programming to meet the FPGA dummy clock requirement for configuration.
21 A write bytes operation requires at least one data byte. If more than 256 bytes are sent to the device, only the last 256 bytes are written to the memory.
22 Erase bulk is applicable to EPCQ-L256 only.
23 Erase die is applicable to EPCQ-L512 and EPCQ-L1024 only.

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