EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Write Disable Operation (04h)

The write disable operation resets the write enable latch bit in the status register. To prevent the memory from being written unintentionally, the write enable latch bit is automatically reset when implementing the write disable operation, and under the following conditions:

  • Power up
  • Write bytes operation completion
  • Write status operation completion
  • Erase bulk operation completion
  • Erase sector operation completion
  • Erase die operation completion
  • Extended quad input fast write bytes operation completion

The following figure shows the timing diagram for the write disable operation.

Figure 10. Write Disable Operation Timing Diagram

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