EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Write Operation Timing

Figure 19. Write Operation Timing Diagram
Table 26.  Write Operation Timing Parameters
Symbol Parameter Min Typical Max Unit
fWCLK Write clock frequency (from the FPGA, download cable, or embedded processor) for write enable, write disable, read status, read device identification, write bytes, erase bulk, erase die, and erase sector operations — — 100 MHz
tCH DCLK high time 4 — — ns
tCL DCLK low time 4 — — ns
tNCSSU Chip select (nCS) setup time 4 — — ns
tNCSH Chip select (nCS) hold time 4 — — ns
tDSU DATA[] in setup time before the rising edge on DCLK 2 — — ns
tDH DATA[] hold time after the rising edge on DCLK 3 — — ns
tCSH Chip select (nCS) high time 50 — — ns
tWB Write bytes cycle time — 0.6 5 ms
tWS Write status cycle time — 1.3 8 ms
tEB Erase bulk cycle time for EPCQ-L256 — 240 480 s
Erase die cycle time for EPCQ-L512
Erase die cycle time for EPCQ-L1024
tES Erase sector cycle time for EPCQ-L256 — 0.7 3 s
Erase sector cycle time for EPCQ-L512
Erase sector cycle time for EPCQ-L1024
tESS Erase subsector cycle time for EPCQ-L256 — 0.25 0.8 s
Erase subsector cycle time for EPCQ-L512
Erase subsector cycle time for EPCQ-L1024
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