EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Write Operation Timing

Figure 19. Write Operation Timing Diagram
Table 26.  Write Operation Timing Parameters
Symbol Parameter Min Typical Max Unit
fWCLK Write clock frequency (from the FPGA, download cable, or embedded processor) for write enable, write disable, read status, read device identification, write bytes, erase bulk, erase die, and erase sector operations 100 MHz
tCH DCLK high time 4 ns
tCL DCLK low time 4 ns
tNCSSU Chip select (nCS) setup time 4 ns
tNCSH Chip select (nCS) hold time 4 ns
tDSU DATA[] in setup time before the rising edge on DCLK 2 ns
tDH DATA[] hold time after the rising edge on DCLK 3 ns
tCSH Chip select (nCS) high time 50 ns
tWB Write bytes cycle time 0.6 5 ms
tWS Write status cycle time 1.3 8 ms
tEB Erase bulk cycle time for EPCQ-L256 240 480 s
Erase die cycle time for EPCQ-L512
Erase die cycle time for EPCQ-L1024
tES Erase sector cycle time for EPCQ-L256 0.7 3 s
Erase sector cycle time for EPCQ-L512
Erase sector cycle time for EPCQ-L1024
tESS Erase subsector cycle time for EPCQ-L256 0.25 0.8 s
Erase subsector cycle time for EPCQ-L512
Erase subsector cycle time for EPCQ-L1024

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