EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Read Bytes Operation (03h)

When you execute the read bytes operation, you first shift in the read bytes operation code, followed by a 4-byte addressing mode (A[31..0]). Each address bit is latched in on the rising edge of the DCLK signal. After the address is latched in, the memory contents of the specified address are shifted out serially on the DATA1 pin, beginning with the MSB. When reading back data programmed from a Raw Programming Data File (.rpd), the content is shifted out serially beginning with the LSB. Each data bit is shifted out on the falling edge of the DCLK signal. The maximum DCLK frequency during the read bytes operation is 50 MHz.

Figure 11. Read Bytes Operation Timing Diagram

The first byte address can be at any location. The device automatically increases the address to the next higher address after shifting out each byte of data. When the device reaches the highest address, the address counter restarts at the beginning of the same die, allowing the memory contents to be read out indefinitely until the read bytes operation is terminated by driving the nCS signal high. A complete device reading is done by executing the read operation:

  • two times for EPCQ-L512 devices
  • four times for EPCQ-L1024 devices

If the read bytes operation is shifted in while a write or erase cycle is in progress, the operation is not executed and does not affect the write or erase cycle in progress.

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