Intel® Cyclone® 10 GX FPGA Development Kit User Guide

ID 683696
Date 8/15/2018
Document Table of Contents
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4.9.2. PCIe Interface

The PCIe* x4 Gen2 Hard IP with CvP is implemented in this development kit. The position of the PCIe* channels is fixed by the hard IP. This development kit is a PCIe* add-in card. The PCIe* interface is configured to End-Point.

The PCIe* interface has the following signals:
  • Transceivers, x4, up to 5 Gbps
  • PCIE_REFCLKp/n, 100 MHz from PCIe* system
  • PCIE_SMBUS, 3.3V level-translated to 1.8V with U18
  • PCIE_PERSTn, 3.3V level-translated to 1.8V with U17
  • PCIE_WAKEn, 3.3V level-translated to 1.8V with U17, reserved
The PCIe* width can be selected with Jumper resistors:
  • R506 installed, x1 mode
  • R507 installed, x4 mode, this is the default mode
There are three power rails from PCIe* golden finger connector:
  • +12 V, +/- 8 %, up to 75 W, is used as power of the board
  • +3.3 V, +/- 9 %, up to 10 W, is not used on this board
  • +3.3 Vaux, +/- 9 %, 375 mA max, is not used since wakeup is not supported