Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab Board Information System MAX Control JTAG Chain 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

5.3.2. The System Info Tab

The System Info tab shows the board's current configuration. The tab displays the contents of the Intel® MAX® 10 registers, the JTAG chain, the board's MAC address, and other details stored on the board.

Figure 12. The System Info tab

The following sections describe the controls of the System info tab

Board Information

The Board Information control displays static information about your board:
  • Board Name: Indicates the official name of the board given by BTS
  • Board P/N: Indicates thr part number of the board
  • Serial Number: Indicates the serial number of the board
  • Board Revision: Indicates the revision of the board
  • MAC Address: Indicates MAC Address of the board

System MAX Control

MAX Ver: Indicates the vesion of Intel® MAX® 10 code currently running on the board.

The Intel® MAX® 10 code resides in the <package dir>\examples\max10 directory. Newer revisions of this code may be available on the Intel® Cyclone® 10 GX FPGA Development kit link on the Intel website.

The Intel® MAX® 10 register control allows you to view and change the current Intel® MAX® 10 register values as described in the table below. Change to the register values with the GUI take effect immediately.

Table 19.  MAX 10 Registers
MAX 10 Register Values Description
Configure Resets the system and reloads the FPGA with a design from the CFI flash memory based on the other Intel® MAX® 10 register values. It works only in FPP mode.
PSO Sets the Intel® MAX® 10 PSO register.
PSR Sets the Intel® MAX® 10 PSR register. Allows PSR to determine the page of flash memory to use for FPGA reconfiguration. The numerical values in the list corresponds to the page of flash memory to load during the FPGA configuration.
PSS Displays the Intel® MAX® 10 PSS register value. Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration.

JTAG Chain

The JTAG chain shows all the devices currently in the JTAG chain.

Note: System MAX and FPGA should all be present in the JTAG chain when running BTS GUI.
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