Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches Power Switch DIP Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.5.1. Switches

Power Switch

The Power Switch S14 is at the edge of the card. When the switch stub is at higher position (marked 'OFF'), the power is OFF.

Note: When the board is inserted into a PCIe* slot in computer, the power switch is override. The board is powered ON/OFF with the PCIe* system irrespective of the position of the power switch.

DIP Switches

The DIP switches are on the bottom side of the board, close to the upper edge.

Table 11.  DIP Switch Definition
Board Reference Switch Signal Name Default Value Function
S9 S9.1 USER_DIP0 1 User available Digital Input 0
S9.2 USER_DIP1 1 User available Digital Input 1
S15 S15.1 USER_DIP2 1 User available Digital Input 2
S15.2 USER_DIP3 1 User available Digital Input 3
S6 S6.1 CFG_M10_PGM0 1 Reserved, No Function
S6.2 CFG_M10_PGM0 1
S1 S1.1 C10_MSEL0 1 Intel® Cyclone® 10 GX MSEL
S1.2 C10_MSEL1 1
S3 S3.1 Si5340_INSEL0 1

Input selection for clock generator chip, the Si5332 on this board

[INSEL1, INSEL0] values:

01 - internal oscillator

10- external reference input from SMB

Set to 01 by default

S3.2 Si5340_INSEL1 0
S2 S2.1 CLKBUF_SEL 0

Set the input source of Si53307

0: Use CLKIN0

1: Use CLKIN1

Fixed to '0'
S2.2 Si570_OE 1

Enable the output of Si570 (Y2)

0: Output disabled

1: Output enabled

Fixed to '1'
S5 S5.1 FMC_JTAGEN 1

Enable FMC Card JTAG

0: Isolate FMC card JTAG from the chain

1: Add FMC Card JTAG into the chain
S5.2 C10_JTGEN 1

Enable Intel® Cyclone® 10 GX FPGA JTAG

0: Isolate FPGA JTAG from the chain

1: Add FPGA JTAG into the chain
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