Intel® Cyclone® 10 GX FPGA Development Kit User Guide

ID 683696
Date 8/15/2018
Document Table of Contents
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5.3.7. The DDR3 Tab

This tab allows you to read and write DDR3 memory on your board.

Figure 18. The DDR3 Tab

The following sections describe the controls on the DDR3 tab.


Initiates DDR3 memory transaction performance analysis.


Terminates transaction performance analysis.

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read and Total performance bars: Shows the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps), Read(MBps) and Total(MBps): Show the number of bytes of data analayzed per second.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected: Displays the number of data errors detected in the hardware.
  • Inserted: Displays the number of errors inserted into the transaction stream.
  • Insert: Inserts a one-word error into the transaction stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected errors and Inserted errors counters to zeroes.

Address Range (Bytes)

Determines the number of bytes to use in each iteration of reads and writes.