Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 11/11/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Software and Driver Installation
2.2. Handling the Board x
2.2.1. Handling the DIP Switches
2.3. Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Development Kit 2.3.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Default Switch and Jumper Settings 3.2. Powering Up the Development Kit
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The Sys Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab Status Control PMA Setting Data Type Error Control Run Control 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Clock Controller 4.3.9. Power Monitor
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Push Buttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe* Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Safety and Regulatory Compliance Information x
B.1. Safety and Regulatory Information B.2. Compliance Information
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Safety and Regulatory Compliance Information

4.3.5. The XCVR Tab

The XCVR tab allows you to perform loopback tests on the PCIe* and SFP+ ports.

Figure 10. The XCVR Tab

Status

The Status control displays the following status information during a loopback test:
  • PLL lock: Shows the PLL locked or unlocked state.
  • Pattern sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
  • Details: Shows the PLL lock, pattern sync status and number of errors for a single channel.

Control

Use the following controls to select an interface to apply PMA settings, data type, and error control:
  • PCIe x4
  • SFP+ x2

PMA Setting

Allows you to make changes to the PMA parameters that affect the active transceiver interface. The following settings are available for analysis:
  • Serial Loopback: Routes signals between the transmitter and the receiver.
  • VOD: Specifies the voltage output differential of the transmitter buffer.
  • Pre-emphasis tap:
    • 1st Pre: Specifies the amount of pre-emphasis on the pre-tap of the transmitter buffer.
    • 2nd Pre: Specifies the amount of pre-emphasis on the second pre-tap of the transmitter buffer.
    • 1st Post: Specifies the amount of pre-emphasis on the first post tap of the transmitter buffer.
    • 2nd Post: Specifies the amount of pre-emphasis on the second post tap of the transmitter buffer.
  • Equalizer: Specifies the AC gain setting for the receiver equalizer in four stage mode.
  • DC gain: Specifies the DC gain setting for the receiver equalizer in four stage mode.
  • VGA: Specifies the VGA gain value.
Figure 11. PCIe x4—PMA Setting

Data Type

The Data Type control specifies the type of data contained in the transactions. Select the following data types for analysis:
  • PRBS7: Selects pseudo-random 7-bit sequences.
  • PRBS15: Selects pseudo-random 15-bit sequences.
  • PRBS23: Selects pseudo-random 23-bit sequences.
  • PRBS 31: Selects pseudo-random 31-bit sequences.
  • high_freq: Selects highest frequency divide-by-2 data pattern 10101010.
  • low_freq: Selects lowest frequency divide-by-33 data pattern.

Error Control

This control displays data errors detected during analysis and allows you to insert errors:
  • Detected Errors: Displays the number of data errors detected in the hardware.
  • Inserted Errors: Displays the number of errors inserted into the transmit data stream.
  • Insert: Inserts a one-word error into the transmit data stream each time you click the button. Insert is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors and Inserted Errors counters to zeroes.

Run Control

  • Start: Initiates the selected ports transaction performance analysis.
    Note: Always click Clear before Start.
  • Stop: Terminates transaction performance analysis.
  • TX and RX performance bars: Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
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