Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

A.8. Power

This development kit is powered by a +12 V power source. The power is one of the following:
  • PCIe* golden finger from PCIe* system
  • ATX 2x4 or external AC/DC adapter
Attention: The ATX 2x4 and external adapter cannot be used simultaneously. The ATX 2x4 can work together with the PCIe* system power input to provide power higher than 25 W.

Power Distribution

Figure 22. Power Distribution Scheme for Power Solution 2 (DK-DEV-10CX220-B)
Table 18.  Power Solution 2
Power Group Power Rail Generated From (V) Maximum Current (A) Manufacturing Part
0 3.3V for MAX® 10 12 0.65 MPM3632SGPQ-C879-Z
5 V for Temperature Sensor 12 0.20 MPM3612GLQ-C879-Z
1 0.9 V 12 16.18 MPM3690GBF-50D-0011
3.3 V 12 12.39 MPM3695GRF-25-0037
2 0.95 V 3.3 1.53 MPM3650CGQW-C879-Z
3 1.8 V 3.3 1.54 MPM3650CGQW-C879-Z
4 1.8 V 3.3 1.54 MPM3650CGQW-C879-Z
1.5 V 3.3 0.75 MPM3650CGQW-C879-Z
VADJ 3.3 1.83 MPM3650CGQW-C879-Z
2.5 V for clock 3.3 4.00 MP20051DQ-LF-C879-Z
2.5 V for GigE 3.3 0.22 MPM3804GG-C879-Z
1 V for GigE 3.3 0.40 MPM3804GG-C879-Z
5 V for USB3.1 12 0.30 MPM3632SGPQ-C879-Z
VTT 1.5 1.50 TPS51200DRCR
Softstart — — LTC4365CDDB-1#TRMPBF
Figure 23. Power Distribution Scheme for Power Solution 1 (DK-DEV-10CX220-A)
Table 19.  Power Solution 1—Enpirion Power Regulators
Power Group Power Rail Generated From (V) Maximum Current (A) Intel® Enpirion® Part
0 3.3 V for MAX® 10 12 0.65 ER3110
5 V for EM2130 12 0.20 ER3105
1 0.9 V 12 16.18 EM2130L
3.3 V 12 12.39 EM2130H
2 0.95 V 3.3 1.53 EN6337
3 1.8 V 3.3 1.54 EN6337
4 1.8 V 3.3 0.75 EN6337
1.5 V 3.3 1.83 EN6337
VADJ 3.3 4.00 EN6347
2.5 V for clock 3.3 0.22 EY1501
2.5 V for GigE 3.3 0.40 EP5348
1 V for GigE 3.3 0.30 EP5348
5 V for USB3.1 12 1.50 ER2120
VTT 1.5 0.6 EV1320
Softstart — — ES1010
Level Two Title