4.4. FPGA Configuration
The JTAG topology of the board is shown in the figure below. An on-board USB Blaster is implemented with the Intel® MAX® 10. It is in the form of a micro-USB type-B connector (J9).
The system Intel® MAX® 10 device itself can be configured through on-board USB port or an external USB-Blaster II header. the 2x5 header for Intel® MAX® 10 is not mounted by default.
A secondary Intel® MAX® 10 device is used for PFL configuration mode. This CFG Intel® MAX® 10 is configured with on-board USB port.
The Intel® Cyclone® 10 GX FPGA device is configured with on-board USB port or an external USB-Blaster II header.
The FMC interface also has a JTAG interface. The FMC JTAG can also be included into the JTAG chain.
The Intel® Cyclone® 10 GX device JTAG and FMC JTAG can be put included or isolated from the JTAG chain by setting a DIP switch S5.
|S5.1||FMC_JTAGEN||ON - Disable JTAG|
|S5.2||C10_JTAGEN||ON - Disable JTAG|
The Intel® Cyclone® 10 GX FPGA device can be configured using different modes. Mode selection can be done using DIP switch S1.
|Configuration Scheme||VCCPGM (V)||Power-On Reset Delay||Valid MSEL [2:0]|
|JTAG-based Configuration||-----||------||Use any valid MSEL pin settings given below|
|AS (x1 and x4)||1.8||Fast||010|
|PS and FPP (x8, x16, x32)||1.2 / 1.5 / 1.8||Fast||000|
MSEL2 is tied to GND
ON - '0'
The Intel® Cyclone® 10 GX FPGA device is configured with two modes: ASx4 or FPP x16. The AS x4 mode uses an EPCQ-L 1024 to store the image. A dedicated Intel® MAX® 10 device is used to implement PFL. It interfaces with two pieces of x16 parallel NOR flash devices to get a x32 bus width. The highest density is 2 Gb. The flash interface works at 3.3 V and various NOR flashes from different vendors can be used with this board.
Micron MT28EW01GABA1LPC-0SITES is installed in manufacturing by default. 2 Gb is provided with the board.
For the Intel® Cyclone® 10 GX FPGA device, the image size is less than 85 Mb. Multiple images can be stored and selected by the user. The image to be used can be selected with a group of Push Buttons and LEDs.
- Cycling images by pushing button S7
- CFG Intel® MAX® 10 device displays current number to be used with LEDs D16-D18
- Initiate the reconfiguration by pushing button S12
|Switch / LED||Signal||Note|
|D16||PGM_LED0||PGM_LED [2:0] indicates the program to be used|
A group of Side Bus signals are defined between Intel® MAX® 10 and Intel® Cyclone® 10 GX FPGA device to provide a higher speed access through on-board USB-Blaster. This interface is reserved in harwdare.