Intel® Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing the Quartus Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Board Overview 4.2. Cyclone 10 GX FPGA 4.3. MAX 10 System Controller 4.4. FPGA Configuration 4.5. Status and User I/O Elements 4.6. Clocks 4.7. Memory 4.8. Power 4.9. Transceivers Interfaces and Communication Ports
4.5. Status and User I/O Elements x
4.5.1. Switches 4.5.2. Pushbuttons 4.5.3. LEDs
4.7. Memory x
4.7.1. EMIF with DDR3 4.7.2. QSPI Flash
4.9. Transceivers Interfaces and Communication Ports x
4.9.1. Transceiver Channels 4.9.2. PCIe Interface 4.9.3. SFP+ Interface 4.9.4. USB3.1 Type-C Interface Parameters of USB3.1 4.9.5. FPGA Mezzanine Card (FMC) Interface 4.9.6. 10/100/1000Base-T Ethernet Connector 4.9.7. I2C/PMBUS
5. Board Test System x
5.1. Preparing the Board 5.2. Running the Board Test System 5.3. Using the Board Test System
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The XCVR Tab 5.3.6. The FMC Tab 5.3.7. The DDR3 Tab 5.3.8. Power Monitor 5.3.9. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. Document Revision History for Intel® Cyclone® 10 GX FPGA Development Kit User Guide
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.9.4. USB3.1 Type-C Interface

A USB3.1 Type-C interface (J8) is provided on the PCIe* bracket. The interface supports SuperSpeed up to 10 Gbps as well as the backward compatible support of USB2.0.

Figure 7. USB3.1 Type-C Block Diagram

The Type-C connector provides any orientation insertion of the cable. To support this feature, a Texas Instruments DRP port Controller and SuperSpeed 2:1 MUX HD3SS3220 is used. The port is configured in DRP mode. The controller detects the orientation of the plugged cable and multiplexes the transceiver of the FPGA to two SuperSpeed interfaces. It also determines if the port is an Upstream Facing Port (UFP) or a Downstream Facing Port (DFP). It controls the power switch to feed the power to cable when in DFP mode. HD3SS3220 is controlled by the FPGA through a dedicated I2C bus.

Parameters of USB3.1

  • I2C address is 7'b110_0111 by default. It can be changed to 7'b100_0111 by installing R199 and removing R198
  • Port mode is Dual Role Port (DRP) by default. It can be chnaged to DFP if R177 is installed, or UFP if R178 is installed.
  • Current Advertisement is 1.5A
A USB3.1 Redriver TUSB1002 is used to condition the high-speed signal because of the degradation caused by the 2:1 mux and to support the 10 Gbps SuperSpeed Plus. The equalization gain and VOD gain of TUSB1002 are set by resistors. The default settings are:
  • EQ for channel 1: 5.5 dB
  • EQ for channel 2: 5.5 dB
  • VOD Gain: 0 for both channels with linear range 1200 mV.

The resistors are set in pull down mode on the board. Other configurations are available by changing the pulling resistors. EQ configurations with pin level "1" are not available.

The power of USB VBUS is controlled with a Texas Instruments power switch TPS25910. The voltage is 5 V and the maximum current is 1.5 A. The power control pin to the TPS25910 is connected to the USB_ID output of HD3SS3220. The power is applied to VBUS only when the port is in DFP mode. The power application can be controlled by the FPGA too. The USB_PWEN signal is active high because of the NMOS inverter.

USB_ID pin on HD3SS3220 indicates the port is linked as a power source (DFP), or dual-role (DRP) acting as source (DFP). USB_ID is connected to the FPGA as well as TPS25910 and USB3320.

Backward support for USB2.0 is implemented with Microchip's USB3320 USB PHY. It interfaces with the FPGA through ULPI interface. The reference clock mode for ULPI is FPGA clock output to USB3320.

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