5.1. Preparing the Board
Several designs are provided to test the major board features. Each design provides data for one or more tabs in the application. The Configure Menu identifies the appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears that allows you to exercise the related board features. Highlights appear in the board picture around the corresponding components.
The BTS communicates over the JTAG bus to a test design running in the FPGA. The BTS and Power Monitor share the JTAG bus with other applications like the Nios® II debugger and the Signal Tap II Embedded Logic Analyzer. Because the BTS is designed based on the Intel® Quartus® Prime software, be sure to close other applications before you use the BTS.
The BTS relies on the Intel® Quartus® Prime software's specific library. Before running the BTS, open the Intel® Quartus® Prime software to automatically set the environment variable $QUARTUS_ROOTDIR. The BTS uses this environment variable to locate the Intel® Quartus® Prime library. The version of Intel® Quartus® Prime software set in the QUARTUS_ROOTDIR environment variable should be newer than version 14.1. For example, the Development Kit Installer version 15.1 requires that the Intel® Quartus® Prime software 14.1 or later version to be installed.
Also, to ensure that the FPGA is configured successfully, you should install the latest Intel® Quartus® Prime software that can support the silicon on the development kit. For this board, we recommend you install Intel® Quartus® Prime version 184.108.40.206.
Please refer to the README.txt file for more information in the examples\board_test_system directory.