| 2025.11.11 |
- Updated the Overview chapter:
- Updated Recommended Operating Conditions.
- Updated the Getting Started chapter:
- Retitled topic Quartus® Prime Software and Driver Installation to Software and Driver Installation.
- Retitled topic Development Kit Package to Installing the Development Kit.
- Added new topics:
- Before you Begin
- Handling the Board
- Handling the DIP Switches
- Installing the Quartus® Prime Pro Edition Software
- Installing the Altera® SoC EDS
- Installing the Intel® FPGA Download Cable
- Updated the Development Kit Setup chapter:
- Updated and retitled topic Setting up the Development Kit to Powering Up the Development Kit.
- Updated the Board Test System chapter:
- Updated Running the Board Test System.
- Retitled topic The System Info Tab to The Sys Info Tab.
- Restructured and retitled appendix chapter Additional Information to Safety and Regulatory Compliance Information.
- Updated document for the latest branding standards.
- Made editorial edits throughout the document.
|
| 2024.08.09 |
- Updated the Overview section:
- Added new table: Ordering Information.
- Added new Figures: Cyclone® 10 GX FPGA Development Kit (Power Solution 2)—Top View and Cyclone® 10 GX FPGA Development Kit (Power Solution 1)—Top View.
- Retitled the General Development Kit Description topic to Feature Summary.
- Added new topic—Bock Diagram.
- Merged content in Handling the Board into Recommended Operating Conditions.
- Updated Installing the Quartus Prime Software:
- Retitled the Installing the Quartus Prime Software topic to Quartus Prime Software and Driver Installation.
- Merged content in Installing the Intel FPGA Download Cable Driver into Quartus Prime Software and Driver Installation.
- Updated Board Overview:
- Updated Figure: Cyclone® 10 GX FPGA Development Kit Block Diagram.
- Updated Table: Board Components Table.
- Updated Cyclone 10 GX FPGA:
- Updated the description for C10_CS0n, C10_AS_D[0:3], and C10_DCLK in Table: Cyclone® 10 GX FPGA I/O Resources Table.
- Updated FPGA Configuration:
- Updated topic description.
- Updated Figures: JTAG Topology Block Diagram and FPGA Configuration Scheme Block Diagram.
- Updated Power:
- Retitled the Power Distribution Scheme figure to Power Distribution Scheme for Power Solution 1.
- Added new Figure: Power Distribution Scheme for Power Solution 2.
- Added new Table: Power Solution 2.
- Updated I2C/PMBUS:
- Retitled the I2C Bus Topology figure to I2C Bus Topology for Power Solution 1.
- Added new figure: I2C Bus Topology for Power Solution 2.
- Updated Board Test System:
- Updated Preparing the Board.
- Removed Figure: About BTS.
- Updated the following figures:
- BTS GUI
- The System Info Tab
- The GPIO Tab
- The Flash Tab
- The XCVR Tab
- The FMC Tab
- The DDR3 Tab
|
| 2018.08.15 |
Updated LEDs. The D19, D20, D21, D22 board reference function updated to '1 to light, output from FPGA'. |
| 2018.03.06 |
- In Default Switch and Jumper Settings, updated value for S3.1 in DIP Switch Settings table to OPEN/OFF/1.
- In Switches, in DIP Switch Settings table, updated default value of S3.1 to 1. Changed values in S3 description to 01 - Internal Oscillator. Set to 01 by default.
|
| 2017.12.18 |
Initial release. |