Cyclone® 10 GX FPGA Development Kit User Guide

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ID 683696
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide A. Development Kit Components B. Additional Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Quartus® Prime Software and Driver Installation 2.2. Development Kit Package
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Using the Board Test System
4.3. Using the Board Test System x
4.3.1. The Configure Menu 4.3.2. The System Info Tab 4.3.3. The GPIO Tab 4.3.4. The EPCQ Tab 4.3.5. The XCVR Tab 4.3.6. The FMC Tab 4.3.7. The DDR3 Tab 4.3.8. Power Monitor 4.3.9. Clock Controller
A. Development Kit Components x
A.1. Board Overview A.2. Cyclone® 10 GX FPGA A.3. MAX 10 System Controller A.4. FPGA Configuration A.5. Status and User I/O Elements A.6. Clocks A.7. Memory A.8. Power A.9. Transceivers Interfaces and Communication Ports
A.5. Status and User I/O Elements x
A.5.1. Switches A.5.2. Pushbuttons A.5.3. LEDs
A.7. Memory x
A.7.1. EMIF with DDR3 A.7.2. QSPI Flash
A.9. Transceivers Interfaces and Communication Ports x
A.9.1. Transceiver Channels A.9.2. PCIe Interface A.9.3. SFP+ Interface A.9.4. USB3.1 Type-C Interface A.9.5. FPGA Mezzanine Card (FMC) Interface A.9.6. 10/100/1000Base-T Ethernet Connector A.9.7. I2C/PMBUS
B. Additional Information x
B.1. Safety and Regulatory Information B.2. Compliance and Conformity Statements
B.1. Safety and Regulatory Information x
B.1.1. Safety Warnings B.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Document Revision History for the Cyclone® 10 GX FPGA Development Kit User Guide
A. Development Kit Components
B. Additional Information

3.2. Default Switch and Jumper Settings

This section lists the default factory switch settings for the Cyclone® 10 GX FPGA Development Kit
Table 4.  DIP Switch Settings
Board Label Switch Default Position Function
S1 S1.1 OPEN/OFF/1 Cyclone® 10 GX GX FPGA MSEL
S1.2 OPEN/OFF/1
S2 S2.1 CLOSE/ON/0 Select clock from Si570 for Si53307's output
S2.2 OPEN/OFF/1 Enable the output of Si570
S3 S3.1 OPEN/OFF/1 Select internal oscillator as the PLL reference of Si5332
S3.2 CLOSE/ON/0
S5 S5.1 OPEN/OFF/1 Enable FMC card JTAG
S5.2 OPEN/OFF/1 Enable Cyclone® 10 GX FPGA JTAG
S6 S6.1 OPEN/OFF/1 Reserved, no function defined
S6.2 OPEN/OFF/1 Reserved, no function defined
S9 S9.1 OPEN/OFF/1 User available Digital Input 0
S9.2 OPEN/OFF/1 User available Digital Input 1
S15 S15.1 OPEN/OFF/1 User available Digital Input 2
S15.2 OPEN/OFF/1 User available Digital Input 3
Level Two Title