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5.3.1. The Configure Menu
5.3.2. The System Info Tab
5.3.3. The GPIO Tab
5.3.4. The EPCQ Tab
5.3.5. The XCVR Tab
5.3.6. The FMC Tab
5.3.7. The DDR3 Tab
5.3.8. Power Monitor
5.3.9. Clock Controller
Serial Port Registers
Target Frequency (MHz)
fXTAL
Default
Set
F_vco
Frequency
Divider
Disable
Read
Import
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Ixiasoft
5.3.9. Clock Controller
The Clock Controller application sets the Si5332 programmable oscillators to any frequency between 5 MHz and 312.5 MHz differential.
The Clock Controller application sets the Si570 programmable oscillators to any frequency between 10 MHz and 725 MHz.
The Clock Control communicates with the Intel® MAX® 10 on the board through the JTAG bus. The programmable oscillator are connected to the Intel® MAX® 10 device through a 2-wire serial bus.
Figure 20. Clock Controller - Si570
Serial Port Registers
Shows the current values from the Si570 registers for frequency configuration.
Target Frequency (MHz)
Allows you to specify the frequency of the clock. Legal values are between 10 MHz and 725 MHz with eight digits of precision to the right of the decimal point. For example, 421.31259873 is possible within 100 parts per million (ppm). The Target Frequency control works in conjunction with the Set control.
fXTAL
Shows the calculated internal fixed-frequency crystal based on the serial port register values.
Default
Sets the frequency for the oscillator associated with the active tab back to its default value. This can also be accomplished by power cycling the board.
Set
Sets the programmable oscillator frequency for the selected clock to the value in the Target Frequency control for the programmable oscillators. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Intel® recommends resetting the FPGA logic after changing frequencies.
Figure 21. Clock Controller - Si5332
Si5332 tab displays the same GUI controls for each clock generators. The Si5332 is a high-performance, low-jitter clock generator capabale of synthesizing five independent banks for user-programmable clock frequencies up to 312.5 MHz.
Note: Currently, only OUT0 and OUT1 can support fractional synthesis output for this board. If you want to change the divider setting, you should use Silicon Laboratories' ClockBuilder tool to generate the register map and use import function on this application.
The controls of the clock controller are described below:
F_vco
Displays the generating signal value of the voltage-controlled oscillator.
Frequency
Allows you to specify the frequency of the clock MHz.
Divider
Display the divider mode and value currently being used on this board.
Disable
Allows you to disable a single output.
Read
Reads the current frequency setting for the oscillator.
Set
Sets the programmable oscillator frequency for the selected clock to the value in OUT0, OUT1, OUT4, OUT6 and OUT7 controls for the Si5332. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this period. Intel® recommends resetting the FPGA logic after changing frequencies.
Import
Import register map file generated from Silicon Laboratories ClockBuilder Desktop.