Intel® Cyclone® 10 GX FPGA Development Kit User Guide

ID 683696
Date 8/15/2018
Document Table of Contents

4.6. Clocks

Figure 5. Clock Distribution

The Intel® Cyclone® 10 GX FPGA local clocks are generated with Si570 + Si53307 + Si5332.

Si570 is a programmable oscillator. It is configurable with an I2C interface at address 7'b110_0110. Si53307 is a clock buffer. With Si570 + Si53307, a high frequency reference clock at frequency up to 725 MHz is available for Intel® Cyclone® 10 GX FPGA Transceiver. Other clocks are generated with an programmable clock generator Si5332 at I2C address 7'b110_1010.

Features of Si5332

  • Output frequency Range: 5 MHz to 312.5 MHz differential
  • Input frequency Range: 10 MHz to 250 MHz differential, 16 MHz to 30 MHz external crystal
  • Embedded 50 MHz crystal option for 8 or 12 port devices
  • MultiSynth technology enables any frequency synthesis on any output up to 250 MHz
  • Highly configurable output path featuring a cross-point multiplexer
    • Up to three independent fractional synthesis output paths
    • Up to five independent integer dividers
    • The Input Reference Clock
  • Low Phase Jitter: 400 fs rms max
  • Programmable spread spectrum
  • 1.8 V, 2.5 V, 3.3 V core VDD
  • 1.8 V, 2.5 V, 3.3 V differential output

A local free running 100 MHz oscillator is used to generate the reference clock for calibration. This clock is also used by ASx4 configuration. A free running 50 MHz oscillator is used to generate a reference clock for FPGA core.

The Intel® MAX® 10 works with free running 50 MHz oscillator. Adjusting the variable clocks does not affect the working of the Intel® MAX® 10 device.