Cyclone® V Device Overview

ID 683694
Date 5/07/2018
Document Table of Contents

Package Plan

Table 15.  Package Plan for Cyclone® V ST Devices
  • The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
  • Transceiver counts shown are for transceiver ≤5 Gbps . 6 Gbps transceiver channel count support depends on the package and channel usage. For more information about the 6 Gbps transceiver channel count, refer to the Cyclone® V Device Handbook Volume 2: Transceivers.
Member Code


(31 mm)

D5 288 181 9 11
D6 288 181 9 11
11 If you require CPRI (at 4.9152 Gbps) and PCIe Gen2 transmit jitter compliance, Intel recommends that you use only up to seven full-duplex transceiver channels for CPRI, and up to six full-duplex channels for PCIe Gen2. The CMU channels are not considered full-duplex channels.