Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

PCS Features

The Cyclone® V core logic connects to the PCS through an 8, 10, 16, 20, 32, or 40 bit interface, depending on the transceiver data rate and protocol. Cyclone® V devices contain PCS hard IP to support PCIe Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO® (SRIO), and Common Public Radio Interface (CPRI).

Most of the standard and proprietary protocols from 614 Mbps to 6.144 Gbps are supported.

Table 23.  Transceiver PCS Features for Cyclone® V Devices
PCS Support

Data Rates (Gbps)

Transmitter Data Path Feature Receiver Data Path Feature
3-Gbps and 6-Gbps Basic 0.614 to 6.144
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Transmitter bit-slip
  • Word aligner
  • Deskew FIFO
  • Rate-match FIFO
  • 8B/10B decoder
  • Byte deserializer
  • Byte ordering
  • Receiver phase compensation FIFO

PCIe Gen1

(x1, x2, x4)

2.5 and 5.0
  • Dedicated PCIe PHY IP core
  • PIPE 2.0 interface to the core logic
  • Dedicated PCIe PHY IP core
  • PIPE 2.0 interface to the core logic

PCIe Gen2

( x1, x2, x4)12
GbE 1.25
  • Custom PHY IP core with preset feature
  • GbE transmitter synchronization state machine
  • Custom PHY IP core with preset feature
  • GbE receiver synchronization state machine
XAUI 13 3.125
  • Dedicated XAUI PHY IP core
  • XAUI synchronization state machine for bonding four channels
  • Dedicated XAUI PHY IP core
  • XAUI synchronization state machine for realigning four channels
HiGig 3.75
SRIO 1.3 and 2.1 1.25 to 3.125
  • Custom PHY IP core with preset feature
  • SRIO version 2.1-compliant x2 and x4 channel bonding
  • Custom PHY IP core with preset feature
  • SRIO version 2.1-compliant x2 and x4 deskew state machine
SDI, SD/HD, and 3G-SDI 0.2714, 1.485, and 2.97 Custom PHY IP core with preset feature Custom PHY IP core with preset feature
JESD204A 0.312515 to 3.125
Serial ATA Gen1 and Gen2 1.5 and 3.0
  • Custom PHY IP core with preset feature
  • Electrical idle
  • Custom PHY IP core with preset feature
  • Signal detect
  • Wider spread of asynchronous SSC
CPRI 4.1 16 0.6144 to 6.144
  • Dedicated deterministic latency PHY IP core
  • Transmitter (TX) manual bit-slip mode
  • Dedicated deterministic latency PHY IP core
  • Receiver (RX) deterministic latency state machine
OBSAI RP3 0.768 to 3.072
V-by-One HS Up to 3.75 Custom PHY IP core
  • Custom PHY IP core
  • Wider spread of asynchronous SSC
DisplayPort 1.2 17 1.62 and 2.7
12 PCIe Gen2 is supported for Cyclone V GT and ST devices. The PCIe Gen2 x4 support is PCIe-compatible.
13 XAUI is supported through the soft PCS.
14 The 0.27-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric.
15 The 0.3125-Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric.
16 High-voltage output mode (1000-BASE-CX) is not supported.
17 Pending characterization.
Level Two Title