Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused receiver PMA as an additional transmit PLL.
|Backplane support||Driving capability up to 6.144 Gbps|
|PLL-based clock recovery||Superior jitter tolerance|
|Programmable deserialization and word alignment||Flexible deserialization width and configurable word alignment pattern|
|Equalization and pre-emphasis||
|Ring oscillator transmit PLLs||614 Mbps to 6.144 Gbps|
|Input reference clock range||20 MHz to 400 MHz|
|Transceiver dynamic reconfiguration||Allows the reconfiguration of a single channel without affecting the operation of other channels|
Did you find the information on this page useful?