Cyclone® V Device Overview

ID 683694
Date 5/07/2018
Document Table of Contents

PMA Features

To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused receiver PMA as an additional transmit PLL.

Table 22.  PMA Features of the Transceivers in Cyclone V Devices
Features Capability
Backplane support Driving capability up to 6.144 Gbps
PLL-based clock recovery Superior jitter tolerance
Programmable deserialization and word alignment Flexible deserialization width and configurable word alignment pattern
Equalization and pre-emphasis
  • Up to 14.37 dB of pre-emphasis and up to 4.7 dB of equalization
  • No decision feedback equalizer (DFE)
Ring oscillator transmit PLLs 614 Mbps to 6.144 Gbps
Input reference clock range 20 MHz to 400 MHz
Transceiver dynamic reconfiguration Allows the reconfiguration of a single channel without affecting the operation of other channels