Cyclone® V Device Overview

ID 683694
Date 5/07/2018
Document Table of Contents

PCIe* Gen1 and Gen2 Hard IP

Cyclone® V GX, GT, SX, and ST devices contain PCIe* hard IP that is designed for performance and ease-of-use. The PCIe* hard IP consists of the MAC, data link, and transaction layers.

The PCIe* hard IP supports PCIe* Gen2 and Gen1 end point and root port for up to x4 lane configuration. The PCIe* Gen2 x4 support is PCIe* -compatible.

The PCIe* endpoint support includes multifunction support for up to eight functions, as shown in the following figure. The integrated multifunction support reduces the FPGA logic requirements by up to 20,000 LEs for PCIe* designs that require multiple peripherals.

Figure 9.  PCIe* Multifunction for Cyclone® V Devices

The Cyclone® V PCIe* hard IP operates independently from the core logic. This independent operation allows the PCIe* link to wake up and complete link training in less than 100 ms while the Cyclone® V device completes loading the programming file for the rest of the device.

In addition, the PCIe* hard IP in the Cyclone® V device provides improved end-to-end datapath protection using ECC.