Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Enhanced Configuration and Configuration via Protocol

Cyclone® V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration schemes.

Table 24.  Configuration Schemes and Features Supported by Cyclone® V Devices
Mode Data Width Max Clock Rate (MHz) Max Data Rate (Mbps) Decompression Design Security Partial Reconfiguration18 Remote System Update
AS through the EPCS and EPCQ serial configuration device 1 bit, 4 bits 100 — Yes Yes — Yes
PS through CPLD or external microcontroller 1 bit 125 125 Yes Yes — —
FPP 8 bits 125 — Yes Yes — Parallel flash loader
16 bits 125 — Yes Yes Yes
CvP (PCIe) x1, x2, and x4 lanes — — Yes Yes Yes —
JTAG 1 bit 33 33 — — — —

Instead of using an external flash or ROM, you can configure the Cyclone® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Related Information
18 The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel® sales representatives.
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