Cyclone® V Device Overview

ID 683694
Date 5/07/2018
Document Table of Contents

Clock Networks and PLL Clock Sources

550 MHz Cyclone® V devices have 16 global clock networks capable of up to operation. The clock network architecture is based on Intel® 's global, quadrant, and peripheral clock structure. This clock structure is supported by dedicated clock input pins and fractional PLLs.

Note: To reduce power consumption, the Intel® Quartus® Prime software identifies all unused sections of the clock network and powers them down.

PLL Features

The PLLs in the Cyclone® V devices support the following features:

  • Frequency synthesis
  • On-chip clock deskew
  • Jitter attenuation
  • Programmable output clock duty cycles
  • PLL cascading
  • Reference clock switchover
  • Programmable bandwidth
  • User-mode reconfiguration of PLLs
  • Low power mode for each fractional PLL
  • Dynamic phase shift
  • Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes

Fractional PLL

In addition to integer PLLs, the Cyclone® V devices use a fractional PLL architecture. The devices have up to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two ways:

  • Reduce the number of oscillators that are required on your board by using fractional PLLs
  • Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source

If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design.

The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.