Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Summary of Cyclone® V Features

Table 2.  Summary of Features for Cyclone® V Devices
Feature Description

Technology

  • TSMC's 28-nm low-power (28LP) process technology
  • 1.1 V core voltage

Packaging

  • Wirebond low-halogen packages
  • Multiple device densities with compatible package footprints for seamless migration between different device densities
  • RoHS-compliant and leaded1options

High-performance FPGA fabric

Enhanced 8-input ALM with four registers

Internal memory blocks

  • M10K—10-kilobits (Kb) memory blocks with soft error correction code (ECC)
  • Memory logic array block (MLAB)—640-bit distributed LUTRAM where you can use up to 25% of the ALMs as MLAB memory

Embedded Hard IP blocks

Variable-precision DSP

  • Native support for up to three signal processing precision levels (three 9 x 9, two 18 x 18, or one 27 x 27 multiplier) in the same variable-precision DSP block
  • 64-bit accumulator and cascade
  • Embedded internal coefficient memory
  • Preadder/subtractor for improved efficiency

Memory controller

DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC support

Embedded transceiver I/O

PCI Express* ( PCIe* ) Gen2 and Gen1 (x1, x2, or x4) hard IP with multifunction support, endpoint, and root port

Clock networks

  • Up to 550 MHz global clock network
  • Global, quadrant, and peripheral clock networks
  • Clock networks that are not used can be powered down to reduce dynamic power

Phase-locked loops (PLLs)

  • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB)
  • Integer mode and fractional mode

FPGA General-purpose I/Os (GPIOs)

  • 875 megabits per second (Mbps) LVDS receiver and 840 Mbps LVDS transmitter
  • 400 MHz/800 Mbps external memory interface
  • On-chip termination (OCT)
  • 3.3 V support with up to 16 mA drive strength

Low-power high-speed serial interface

  • 614 Mbps to 6.144 Gbps integrated transceiver speed
  • Transmit pre-emphasis and receiver equalization
  • Dynamic partial reconfiguration of individual channels

HPS

( Cyclone® V SE, SX, and ST devices only)

  • Single or dual-core Arm* Cortex* -A9 MPCore* processor-up to 925 MHz maximum frequency with support for symmetric and asymmetric multiprocessing
  • Interface peripherals—10/100/1000 Ethernet media access control (EMAC), USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface (QSPI) flash controller, NAND flash controller, Secure Digital/MultiMediaCard (SD/MMC) controller, UART, controller area network (CAN), serial peripheral interface (SPI), I2C interface, and up to 85 HPS GPIO interfaces
  • System peripherals—general-purpose timers, watchdog timers, direct memory access (DMA) controller, FPGA configuration manager, and clock and reset managers
  • On-chip RAM and boot ROM
  • HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa
  • FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport front end (MPFE) of the HPS SDRAM controller
  • Arm* CoreSight™ JTAG debug access port, trace port, and on-chip trace storage

Configuration

  • Tamper protection—comprehensive design protection to protect your valuable IP investments
  • Enhanced advanced encryption standard (AES) design security features
  • CvP
  • Dynamic reconfiguration of the FPGA
  • Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and x16 configuration options
  • Internal scrubbing 2
  • Partial reconfiguration 3
1 Contact Intel for availability.
2 The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel sales representatives.
3 The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel® sales representatives.
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