Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multiport SDRAM memory controller, as shown in the following figure.
Figure 11. HPS with Dual-Core Arm* Cortex* -A9 MPCore* Processor
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