Cyclone V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Key Advantages of Cyclone® V Devices

Table 1.   Key Advantages of the Cyclone® V Device Family

Advantage

Supporting Feature

Lower power consumption
  • Built on TSMC's 28 nm low-power (28LP) process technology and includes an abundance of hard intellectual property (IP) blocks
  • Up to 40% lower power consumption than the previous generation device
Improved logic integration and differentiation capabilities
  • 8-input adaptive logic module (ALM)
  • Up to 13.59 megabits (Mb) of embedded memory
  • Variable-precision digital signal processing (DSP) blocks
Increased bandwidth capacity
  • 3.125 gigabits per second (Gbps) and 6.144 Gbps transceivers
  • Hard memory controllers
Hard processor system (HPS) with integrated Arm* Cortex* -A9 MPCore* processor
  • Tight integration of a dual-core Arm* Cortex* -A9 MPCore* processor, hard IP, and an FPGA in a single Cyclone® V system-on-a-chip (SoC)
  • Supports over 128 Gbps peak bandwidth with integrated data coherency between the processor and the FPGA fabric
Lowest system cost
  • Requires only two core voltages to operate
  • Available in low-cost wirebond packaging
  • Includes innovative features such as Configuration via Protocol (CvP) and partial reconfiguration
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