eCPRI Intel® FPGA IP User Guide

ID 683685
Date 12/14/2021
Public

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5.9. External ST Source Interface

Table 35.  Signals of the External ST Source InterfaceAll signals are synchronous to ext_sink_clk.
Signal Name Width (Bits) I/O Direction Description
ext_source_valid 1 Output Avalon® source valid from L2/L3 parser to external user logic.
ext_source_data DATA_WIDTH 6 Output Avalon® source write data from L2/L3 parser to external user logic.
ext_source_sop 1 Output Avalon® source start of packet from L2/L3 parser to external user logic. Indicate the beginning of packet.
ext_sink_eop 1 Output Avalon® source end of packet from L2/L3 parser to external user logic. Indicates the end of packet.
ext_source_empty LOG2(DATA_WIDTH6/8) Output Avalon® source empty from L2/L3 parser to external user logic. Indicates the number of symbols that are empty, that is, do not represent valid data.
ext_source_error 1 Output Avalon® source error from L2/L3 parser to external user logic. A bit mask to mark errors affecting the data being transferred in the current cycle.
6 This is set to 64. This parameter is hidden from user and you can't change it.