eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 12/14/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
6. Registers x
6.1. eCPRI Version Register 6.2. eCPRI Scratch Register 6.3. eCPRI Common Control Register 6.4. eCPRI Message 5 Control Register 6.5. eCPRI TX Error Message Register 6.6. eCPRI RX Error Message Register 6.7. eCPRI Error Mask Message Register 6.8. eCPRI Error Log Message Register 6.9. eCPRI Error Message 5 Compensation Value 0 Register 6.10. eCPRI Error Message 5 Compensation Value 1 Register 6.11. eCPRI Transport Delay 0 Register 6.12. eCPRI Transport Delay 1 Register 6.13. eCPRI Transport Delay 2 Register 6.14. Ethernet Frame Scratch Register 6.15. Source MAC Address <i> Register, where i= 0, 1 6.16. Destination MAC n Address <i> Register, where n= 0, 1, 2, 3, 4, 5, 6, 7 and i= 0, 1 6.17. VLAN Tag Register <i>, where i= 0, 1, 2, 3, 4, 5, 6, 7 6.18. Ethertype Register 6.19. IPv4 Dw0 Register 6.20. IPv4 Dw1 Register 6.21. IPv4 Dw2 Register 6.22. IPv4 Source Address Register 6.23. IPv4 Destination Address Register 6.24. UDP Dw0 Register 6.25. UDP Port Register 6.26. MAC Packet Type Enable Register 6.27. RX Error Register
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

4.2.3. Supported Ethernet Variants

The eCPRI Intel FPGA IP pairs together with the 25G/10G Ethernet. The eCPRI IP is validated together with the 25G Ethernet for Intel® Stratix® 10 designs.

For your Intel® Stratix® 10 designs, you can select 25G Ethernet Intel FPGA IP for H-tile variants and E-tile Hard IP for Ethernet Intel FPGA IP for E-tile variants. When you use these IPs, you must set the following parameter values in the IP parameter editor:
  • Select Ethernet Rate if you use E-tile Hard IP for Ethernet Intel FPGA IP.
    Note: This option is not available with 25G Ethernet Intel FPGA IP. Use Enable 10G/25G dynamic rate switching for 10G data rate.
  • Enable Enable IEEE 1588 parameter to support client PTP message and eCPRI one-way delay measurement. The 25G Ethernet MAC only supports 96-bit (V2) timestamp format.
  • Disable Enable preamble pass-through and Enable TX CRC pass-through parameters.
  • Turn on Enable 10G/25G dynamic rate switching option to switch between 10G and 25G data rates.

For your Intel® Arria® 10 designs, you can use Low Latency Ethernet 10G MAC Intel FPGA IP and 1G/10GbE and 10GBASE-KR PHY Intel FPGA IP to implement MAC and PHY respectively for your Ethernet.

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