CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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Document Table of Contents

5.21. TX_EX_DELAY Register

Table 73.  TX_EX_DELAY Register at Offset 0x50
Bits Field Name Type Value on Reset Description
31:24 tx_msrm_period RW 8'b0 Integration period for Tx buffer extended delay measurement.

Program this field with the user-defined value N, where M/N = ex_delay_clk period / cpri_clkout period.

23 tx_ex_delay_valid RC 1'b0 Indicates that the tx_ex_delay field has been updated.
22:16 Reserved UR0 7'b0
15:0 tx_ex_delay RO 16'b0 Tx buffer extended delay measurement result. Unit is cpri_clkout clock periods.