CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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3.17. Extended Delay Measurement

The CPRI Intel® FPGA IP employs an additional mechanism to measure the delay through the IP core FIFOs to your desired precision. Separate dedicated clocks support this measurement for the RX and TX internal buffers in all variations and for the hard FIFOs present only in Intel® Stratix® 10 variations.