Visible to Intel only — GUID: nik1411442141183
Ixiasoft
Visible to Intel only — GUID: nik1411442141183
Ixiasoft
2.8. Running the Testbench
- In the Quartus® Prime software IP Catalog, select the CPRI Intel® FPGA IP and click Add.
- When prompted, you can specify any output file type (HDL). This setting is relevant only for synthesis and does not impact simulation of the demonstration testbench.
- In the CPRI parameter editor, set the following parameter values:
Table 17. CPRI Intel® FPGA IP Core Variation for Demonstration TestbenchThe testbench scripts require that you set these values in the CPRI parameter editor before you click Generate Example Design. The scripts generate the DUT but they require that you provide the parameter values. Parameter Value Line bit rate (Mbit/s) Any value the device family supports. Synchronization mode Master Operation mode Any available mode Transmitter local clock division factor 1 Number of receiver CDR reference clock(s) 1 Receiver CDR reference clock frequency (MHz) 253.44 if the Line bit rate is 8.11008 or 10.1376 or 12.16512 Gbps and the IP targets the Intel® Stratix® 10 device family
368.64 if the Line bit rate is 24.33024 Gbps and the IP targets the Intel® Stratix® 10 device family
253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets the Intel® Arria® 10 device family
253.44 if the Line bit rate is 8.11008 or 10.1376 Gbps and the IP targets a 28-nm device family
253.44 if the Line bit rate is 8.11008 Gbps and the IP targets Arria® V GZ device family
307.2 for all other cases
Core clock source input Internal or External Recovered clock source PMA if the Line bit rate is 10.1376 Gbps and IP core targets the Stratix V device family; PCS otherwise Receiver soft buffer depth (value shown is log2 of actual depth) 6 Enable line bit rate auto-negotiation Turn off Enable line bit rate auto-negotiation down to 614.4 Mbps Not available Management (CSR) interface standard Avalon® -MM Avalon-MM interface addressing type Word Auxiliary and direct interfaces write latency cycle(s) 0 Enable auxiliary interface Turn on or Turn off Enable resyncronization of CPRI radio frame number to desired value Turn on or Turn off Enable all control word access via management interface Turn off Enable direct Z.130.0 alarm bits access interface Turn off Enable direct ctrl_axc access interface Turn on or Turn off Enable direct vendor specific access interface Turn on or Turn off Enable direct real-time vendor specific interface Turn on or Turn off Enable start-up sequence state machine Turn off Enable protocol version and C&M channel setting auto-negotiation Not available Enable direct IQ mapping interface Turn on or Turn off Enable HDLC serial interface Turn on or Turn off Ethernet PCS interface NONE, MII or GMII L2 Ethernet PCS Tx/Rx FIFO depth (value shown is log2 of actual depth) 8 Enable L1 debug interfaces Turn off Enable Native PHY Debug Master Endpoint (NPDME), transceiver capability, control and status registers access Turn off Enable transceiver PMA serial forward loopback path Turn off Enable parallel forward loopback paths Turn off Enable parallel reversed loopback paths Turn off Enable single-trip delay calibration Not available Enable round-trip delay calibration Turn off Round-trip delay calibration FIFO depth Not available Language for top-level simulation file - Verilog
- VHDL
- In the CPRI parameter editor, click the Generate Example Design button and specify the desired location of the testbench.
- Change directory to <your_ip>/setup_scripts/<simulator_vendor> .
- For Intel Agilex F-tile devices, perform these additional steps:
- Navigate to the <your_ip>/ip_components directory and perform these two commands:
quartus_ipgenerate --run_default_mode_op tb_top -c tb_top
Alternately, you may open the tb_top.qpf project in Intel® Quartus® Prime and perform the compilation until support logic generation stage.quartus_tlg tb_top
- Navigate to the <your_ip>/simulation/setup_scripts directory.
- Perform the following command:
ip-setup-simulation -quartus-project=../ip_components/tb_top.qpf --use-quartus-top-names
- Navigate to the <your_ip>/ip_components directory and perform these two commands:
- If you are using a simulator that requires that you open a user interface, open your target simulator.
Note: You must select a simulator that is supported by the Intel® Quartus® Prime software version you are using.
- Execute the simulation script available for your simulation in the directory.
- In the Mentor Graphics ModelSim simulator, type do msim_commands.do
- You can modify testbench parameters from a file params_list.sv, located at <your_ip>/testbench location.