CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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Document Table of Contents

5.20. RX_DELAY Register

Table 72.  RX_DELAY Register at Offset 0x4C
Bits Field Name Type Value on Reset Description
31:25 Reserved UR0 7'b0
24 rx_buf_resync RW 1'b0 Force receive buffer pointer resynchronization. You can use this register field to resynchronize if, for example, the buffer fill level becomes too high due to due to environmental impacts on the device, such as temperature. Resynchronizing might lead to data loss or corruption.

Do not use this register field to resynchronize after a dynamic CPRI line bit rate change. After a dynamic CPRI line bit rate change the IP core forces resynchronization internally without referring to this register.

23:17 Reserved UR0 7'b0
16 rx_byte_delay RO 1'b0 Current byte-alignment delay. This field is relevant for the Rx path delay calculation.
15:RX_BUF_DEPTH Reserved UR0 0
(RX_BUF_DEPTH -1):0 rx_buf_delay RO 0 Current receive buffer fill level. Unit is 32-bit words. Maximum value is 2RX_BUF_DEPTH-1.