CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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5.26. DELAY_CAL_STD_CTRL2 Register

Table 78.  DELAY_CAL_STD_CTRL2 Register at Offset 0x64 This register is available only in CPRI slave Intel® FPGA IP cores with the single-trip delay calibration feature.

The user provides this information to specify the anticipated or desired duration of the total variable component of the single-trip delay. This value reflects the system requirements.

Bits Field Name Type Value on Reset Description
31:25 Reserved UR0 7'b0
24:16 cal_step_delay RW 9'b0 Additional fractional cpri_clkout clock cycles of delay in step units.
15:8 Reserved UR0 8'b0  
7:0 cal_cycle_delay RW 8'b0 Delay in full cpri_clkout clock cycles.