CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents


Table 82.  DELAY_CAL_STD_STATUS Register at Offset 0x74 This register is available only in CPRI slave Intel® FPGA IP cores with the single-trip delay calibration feature.
Bits Field Name Type Value on Reset Description
31:16 Reserved UR0 16'b0
15:0 cal_current_delay RO 16'b0 Variable delay from the synchronization service access point (SAP) in the CPRI link master to the synchronization SAP in this CPRI slave IP core. Unit is clk_ex_delay clock cycles.

The IP core calculates this value. The Intel® -provided single-trip delay calibration modules use this value to determine the values they write to the cal_step_delay and cal_cycle_delay fields of the IP core's DELAY_CAL_STD_CTRL2 register.

Note: Registers at offset 0x78 and 0x7C are reserved.