CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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Document Table of Contents

5.11. START_UP_TIMER Register

Table 63.  START_UP_TIMER Register at Offset 0x28 This register is available only if you turn on Enable start-up sequence state machine in the CPRI parameter editor.
Bits Field Name Type Value on Reset Description
31:20 Reserved UR0 12'b0
19:0 startup_timer_period RW 20'b0 Threshold value for L1 start-up timer to expire. The unit is cpri_coreclk clock cycles.