CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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5.15. RX_CTRL Register

Table 67.  RX_CTRL Register at Offset 0x38 Frequency differences between the control and status interface clock cpu_clk and the main CPRI Intel® FPGA IP clock cpri_clkout might cause non-zero read latency and more than one clock cycle of write latency when accessing this register.
Bits Field Name Type Value on Reset Description
31:0 rx_ctrl_data RO 32'b0 Most recent received CPRI control word 32-bit section from CPRI hyperframe position Z.x, where x is the index in the rx_ctrl_x field of the CTRL_INDEX register. The rx_ctrl_seq field of the CTRL_INDEX register indicates whether this is the first, second, third, fourth, or fifth such 32-bit section.