CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

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3.16. Auto-Rate Negotiation

If you turn on Enable line bit rate auto-negotiation in the CPRI parameter editor, the auto-rate negotiation control and status interface is available. The CPRI IP provides support for dynamically changing the CPRI line bit rate, but requires that you implement user logic to control the auto-rate negotiation process. You control the process through the auto-rate negotiation control and status interface or the BIT_RATE_CONFIG register at offset 0x0C.

Table 34.  Auto-Rate Negotiation Control and Status Interface Signals

All interface signals are clocked by the cpri_clkout clock.

Signal Name



nego_bitrate_in[5:0] Input CPRI line bit rate to be used in next attempt to achieve frame synchronization, encoded according to the following valid values:
  • 6'b000001: 0.6144 Gbps
  • 6'b000010: 1.2288 Gbps
  • 6'b000100: 2.4576 Gbps
  • 6'b000101: 3.0720 Gbps
  • 6'b001000: 4.9150 Gbps
  • 6'b001010: 6.1440 Gbps
  • 6'b001100: 8.11008 Gbps
  • 6'b010000: 9.8304 Gbps
  • 6'b010100: 10.1376 Gbps
  • 6b'011000: 12.16512 Gbps
  • 6'b110000 : 24.33024 Gbps

This signal has higher priority than the bit_rate field in the BIT_RATE_CONFIG register at offset 0x0C. When this signal has the value of 6'b000000, the CPRI IP core responds to the register field.

nego_bitrate_out[5:0] Output Reflects the current actual CPRI line bit rate.