CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/11/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.29. DELAY_CAL_STD_CTRL5 Register

Table 81.  DELAY_CAL_STD_CTRL5 Register at Offset 0x70 This register is available only in CPRI slave Intel® FPGA IP cores with the single-trip delay calibration feature.
Bits Field Name Type Value on Reset Description
31:17 Reserved UR0 15'b0
16 cal_tx_delay_usr_en RW 1'b0 Enable a CPRI slave Intel® FPGA IP core to receive TX delay information in the cal_tx_delay_usr field.

When the value of this field is 1, the IP core cannot receive TX delay information in incoming CPRI communication.

15:12 Reserved UR0 4'b0
11:0 cal_tx_delay_usr RW 12'b0 TX delay value provided by software. This field is valid only when the cal_tx_delay_usr_en field has the value of 1.

Unit is clk_ex_delay clock cycles.