Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.10.1. Parallel NOR Flash Memory

The Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit has two 1-Gbit CFI compatible asynchronous flash device for non-volatile storage of the FPGA configuration data, board information, test application data and user code space.

Two flash devices are implemented to achieve a 16-bit wide data bus at 16 bits each per device. Both MAX V CPLD and Intel® Stratix® 10 TX FPGA can access this flash device.

MAX V CPLD accesses are for AvST configuration of the FPGA at power-on and board reset events. It uses the PFL Megafunction.

Table 17.  Memory Map of the first 1G NOR Flash Memory (x16)
Block Description Size (KB) Address Range
Reserved 512 0x0750.0000 - 0x0757.FFFF
Reserved 14336 0x0670.0000 - 0x074F.FFFF
Reserved 8192 0x05F0.0000 - 0x06FF.FFFF
Reserved 8192 0x0570.0000 - 0x05EF.FFFF
User hardware1 44032 0x02C0.0000 - 0x056F.FFFF
User hardware0 44032 0x0010.0000 - 0x02BF.FFFF
PFL option bits 256 0x000C.0000 - 0x000F.FFFF
Reserved 256 0x0008.0000 - 0x000B.FFFF
Reserved 256 0x0004.0000 - 0x0007.FFFF
Reserved 256 0x0000.0000 - 0x0003.FFFF
Table 18.  Memory Map of the second 1G NOR Flash Memory (x16)
Block Description Size (KB) Address Range
User hardware2 44032 0x0010.0000 - 0x02BF.FFFF
PFL option bits 256 0x000C.0000 - 0x000F.FFFF
Reserved 256 0x0008.0000 - 0x000B.FFFF
Reserved 256 0x0004.0000 - 0x0007.FFFF
Reserved 256 0x0000.0000 - 0x0003.FFFF
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