Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.1. Development Kit Overview

Figure 2.  Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit Picture
Table 3.  Development Kit Components
Board Reference Type Description
Featured Devices
U39 FPGA Intel® Stratix® 10 TX 280 F2912 FPGA (1ST280EY2F55E1VG)
U13 CPLD System MAX® V CPLD (5M2210ZF256)
U4 FPGA USB Intel® MAX® 10 FPGA (10M04SCU169)
U8 FPGA PWR Intel® MAX® 10 FPGA (10M16SAU169)
General User Input and Output
D12-D15 User LEDs (Green) User LEDs (Green)
D16-D21 MAX® V LEDs (Green) MAX® V LEDs (Green)
S1-S4 User Push Buttons User Push Buttons
SW4 User DIP Switches User DIP
SW5 MAX® V DIP Switch MAX® V DIP Switch
S5-S8 MAX® V Push Buttons MAX® V Push Buttons
Configuration, Status and Setup Elements
J8 Embedded Intel® FPGA Download Cable II Programming Header (uses JTAG mode only) Header to interface external Intel® FPGA Download Cable direct to FPGA (through USB Intel® MAX® 10)
D1-D2 Green LEDs JTAG transmit-Receive Activity
D3-D4 Green LEDs System Console transmit-Receive Activity
D5 Amber LEDs System Power error indicator
D6 Amber LEDs Temperature alert indicator
D7-D11 Ethernet LEDs Ethernet LEDs (TX/RX/LINK)
Clock Circuits
X2 50-MHz Oscillator

This 50-MHz oscillator is the clock source to clock buffer SL18860DC that provides three 50 MHz outputs to the FPGA, MAX® V and UB2 Intel® MAX® 10

X1 50-MHz Oscillator This 50-MHz oscillator provides clock to the PWR Intel® MAX® 10 FPGA
Y1 Transceiver Dedicated Reference Clock/Programmable Oscillator Feed clock for Intel® Stratix® 10 TX device and an LVDS trigger output at board reference J3/​J4. The external input is available at board reference J1 and J2. The default frequency is 156.25 MHz.
U1 High-speed clock buffer Fan-out REFCLKs for Intel® Stratix® 10 TX transceiver banks
U3 Transceiver Dedicated Reference Clock/Programmable PLL Feeds clocks for Intel® Stratix® 10 TX device and an LVDS trigger output at board reference J5​/J6. The default frequencies are 156.25 MHz, 125 MHz, 100 MHz, 322.265625 MHz, 176.5625 MHz, 307.2 MHz.
J30,J32 External core clock input SMA external input at CLKIN_2L
J31,J33 External core clock output SMA external output at PLL_2L_CLKOUT0
J34-J35 External transceiver clock input SMA external input at H-tile 1D bank
J36-J37 External transceiver clock input SMA external input at E-tile 8B bank
J38-J39 External transceiver clock input SMA external input at E-tile 8C bank
J40-J41 External transceiver clock input SMA external input at E-tile 9A bank
J42-J43 External transceiver clock input SMA external input at E-tile 9B bank
J44-J45 External transceiver clock input SMA external input at E-tile 9C bank
Transceiver Interfaces
J15/J17 MXP connector NRZ 28.9 Gbps or PAM4 58 Gbps, 4 channels connected to each MXP connector
J19-J26 2.4 mm RF connector NRZ 28.9 Gbps or PAM4 58 Gbps, 2 channels connected to 2.4 mm RF connector
U30/U78 QSFPDD 1x1 optical transceiver interface PAM4 58 Gbps, 8 channels connected to 400 Gbps module
U32/U75 QSFPDD 1x2 optical transceiver interface NRZ 28.9 Gbps, 8 channels per port connected 200 Gbps module
U36 QSFPDD 2x1 optical transceiver interface NRZ 28.9 Gbps, 8 channels per port connected to both top and bottom 200 Gbps module
J27 FMC+ connector NRZ 28 Gbps, 24 channels connected to FMC+ connector
Memory Devices
U14-U15 Flash Memory Two 1-Gbit Micron MT28EW01GABA1HPC CFI Flash device
Communication Ports
J12 Gigabit Ethernet Port RJ-45 connector which provides a 10/100/1000 Ethernet connection through a Marvell 88E1111 PHY
CN1 USB Type-B connector Connects a type-B USB cable
Power Supply
U47-U48 Two LTM4678s Power regulators for VCC rail
U49 LTM4676A Power regulator for VCCERAM rail
U51 LTM4678 Power regulator for VCCERT rail
U50 LTM4675 Power regulator for VCCR/VCCT rail
U52 LTM4676A Power regulator for 1.8V/VCCH_E rail
U58 EP5348UI Power regulator for 2.4V rail
U60 EN5339 Power regulator for 2.5V rail
U53 LTM4676A Power regulator for 3.3V rail
Level Two Title