Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

3.2. Factory Default Switch and Jumper Settings

This section shows the factory default switch and jumper settings for the Intel® Stratix® 10 TX transceiver signal integrity development kit.
Table 2.  Factory Default Switch Settings
Switch Board Label Default Position Function
SW8 MSEL1 MSEL1=0 MSEL Setting = 0
MSEL2 MSEL2=0 MSEL Setting = 0
SW1-1 Stratix 10 OPEN/OFF Enable Intel® Stratix® 10 in JTAG Chain
SW1-2 MAX V OPEN/OFF Enable MAX® V in JTAG chain
SW1-3 FMC A CLOSE/ON Bypass FMC from JTAG chain
SW1-4 UBMAX_DIP OPEN/OFF UB MAX® V User Dipswitch
SW6-1

OFF = OSC

ON = SMA

OPEN/OFF Select Si549 clock source for U1
SW6-2/3/4 PWRMAX_DIP OPEN/OFF Power MAX® V User Dipswitch
SW7-1 OFF=VCC ISOLATE CLOSE/ON U47/U48 (LTM4680) are enabled in I2C topology
SW7-2 ON=FULL CHAIN CLOSE/ON U47/U48 (LTM4680) are enabled in I2C topology
SW3-1 EN_VCCH_E OPEN/OFF

Enable on-board VCCH_E

regulator
SW3-2 EN_VCCERT OPEN/OFF

Enable on-board VCCERT

regulator
SW2-1 VCCR OPEN/OFF

Enable on-board VCCR

regulator
SW2-2 VCCT OPEN/OFF

Enable on-board VCCT

regulator
SW2-3 VCCERAM OPEN/OFF

Enable on-board VCCERAM

regulator
SW2-4 VCC OPEN/OFF

Enable on-board VCC

regulator
SW5-1 FACTORY_LOAD OPEN/OFF Factory Load Control
SW5-2 MAX5_SWITCH2 OPEN/OFF MAX® V user DIPSwitch
SW5-3 MAX5_SWITCH0 OPEN/OFF MAX® V user DIPSwitch
SW5-4 MAX5_SWITCH1 OPEN/OFF MAX® V user DIPSwitch
SW4-1 S10_UNLOCK OPEN/OFF Intel® Stratix® 10 User DIPSwitch
SW4-2 USER_DIP2 OPEN/OFF Intel® Stratix® 10 User DIPSwitch
SW4-3 USER_DIP1 OPEN/OFF Intel® Stratix® 10 User DIPSwitch
SW4-4 USER_DIP0 OPEN/OFF Intel® Stratix® 10 User DIPSwitch
SW10 SW10 OFF On-board power switch
Level Two Title