Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.2. Intel® Stratix® 10 TX FPGA

The development board features the Intel® Stratix® 10 TX FPGA (1ST280EY2F55E1VG).

Table 4.   Intel® Stratix® 10 TX FPGA I/O Summary
Signal Name I/O Count Description
Configuration
S10_JTAG_TDI/TDO/TCK/TMS 4 JTAG pins
FPGA_MSEL[2:0] 3 Configuration input pins to set configuration scheme
FPGA_CONF_DONE 1 Configuration done pin
FPGA_nSTATUS 1 Configuration status pin
FPGA_INIT_DONE 1 Configuration pin to signify user mode
FPGA_nCONFIG 1 Configuration input pin to reset FPGA
FPGA_OSC_CLK_1 1 125 MHz Clock
FPGA_AS_CLK 1 Configuration Clock for AS configuration schemes
CPU_RESETn 1

Configuration input pin that clears all

device registers
FPGA_CONFIG_D[15:0] 32 Configuration input pin that enables all I/Os
FPGA_AS_DATA[3:0] 4 EPCQL data bus
FPGA_AVST_READY 1 SDM ready for AvST configuration scheme
FPGA_AVST_VALID 1 Data valid for AvST configuration scheme
FPGA_AVST_CLK 1 Configuration Clock for AvST configuration scheme
FPGA_PR_DONE 1 Partial reconfiguration done pin
FPGA_PR_REQUEST 1 Partial reconfiguration request pin
FPGA_PR_ERROR 1 Partial reconfiguration error pin
NPERSTL0 1 Reset pin for left bottom PCIe HIP
FPGA_CvP_DONE 1 CvP configuration done pin
FPGA_SEU_ERR 1 SEU error indicate pin
VCC_SDA/SCL 2 SmartVID I2C bus
VCC_ALERTn 1 SmartVID I2C bus
Transceivers
OIF_SCL[1:0] 2 Optical Management Data Clock 0
OIF_SDA[1:0] 2 Optical Management Data I/O Bi-Directional Data 0
DDQ1x1_modselL 1 DDQ1x1 module select control pin
DDQ1x1_resetL 1 DDQ1x1 module reset control pin
DDQ1x1_Initmode 1 DDQ1x1 initiate mode control pin
DDQ1x1_modprsL 1 DDQ1x1 module present indicator pin
DDQ1x1_intl[1:0] 2 DDQ2x1 module interrupt pin
DDQ1x1_1_modselL 1 DDQ1x1 module select control pin
DDQ1x1_1_resetL 1 DDQ1x1 module reset control pin
DDQ1x1_1_Initmode 1 DDQ1x1 initiate mode control pin
DDQ1x1_1_modprsL 1 DDQ1x1 module present indicator pin
DDQ1x1_1_intl[1:0] 2 DDQ2x1 module interrupt pin
DDQ2x1_modselL[1:0] 2 DDQ2x1 module select control pin
DDQ2x1_resetL[1:0] 2 DDQ2x1 module reset control pin
DDQ2x1_Initmode[1:0] 2 DDQ2x1 initiate mode control pin
DDQ2x1_modprsL[1:0] 2 DDQ2x1 module present indicator pin
DDQ2x1_intl[1:0] 2 DDQ2x1 module interrupt pin
DDQ1x2_modselL[1:0] 2 DDQ1x2 module select control pin
DDQ1x2_resetL[1:0] 2 DDQ1x2 module reset control pin
DDQ1x2_Initmode[1:0] 2 DDQ1x2 initiate mode control pin
DDQ1x2_modprsL[1:0] 2 DDQ1x2 module present indicator pin
DDQ1x2_intl[1:0] 2 DDQ1x2 module interrupt pin
FALAp/n[31:0] 64 FMC+ A LA bank GPIOs
FALAp/n[33:32]_CON 4 FMC+ A LA bank GPIOs
FAHAp/n[23:0] 48 FMC+ A HA bank GPIOs
FAHBp/n[21:0] 44 FMC+ A HB bank GPIOs
FACLKM2CP/N[1:0] 4 FMC+ A general clocks
FACLKBIDIRP/N[3:2] 4 FMC+ A general clocks
FAREFCLKC2MP/N 2 FMC+ A general clocks
FAREFCLKM2CP/N 2 FMC+ A general clocks
FASYNCC2MP/N 2 FMC+ A general clocks
FASYNCM2CP/N 2 FMC+ A general clocks
RZQ_2N 1 RZQ pin for bank 2N
Other Bus
USER_DIP[2:0]/S10_Unlock 4 User Dipswitch bits
USER_LED[3:0] 4 User LED bits
USER_IO[9:0] 10 User IO bits
USER_PB[3:0] 4 User Push Button bits
USB_DATA[7:0] 8 Side bus between Intel® Stratix® 10 and UB2 Intel® MAX® 10
USB_ADDR[1:0] 2 Side bus between Intel® Stratix® 10 and UB2 Intel® MAX® 10
USB_FULL/EMPTY/RESETn 3 Side bus between Intel® Stratix® 10 and UB2 Intel® MAX® 10
USB_OEn/RDn/WRn 3 Side bus between Intel® Stratix® 10 and UB2 Intel® MAX® 10
USB_SCL/SDA 2 Side bus between Intel® Stratix® 10 and UB2 Intel® MAX® 10
ENET_MDIO/MDC/RSTn/INTn 4 10/100/1000M Ethernet port
ENET_SGMII_TX_P/N 2 10/100/1000M Ethernet port
ENET_SGMII_RX_P/N 2 10/100/1000M Ethernet port
I2C_1V8_SCL 1 Intel® Stratix® 10 I2C bus
I2C_1V8_SDA 1 Intel® Stratix® 10 I2C bus
Temperature
OVERTEMPn_1V8 1 Intel® Stratix® 10 over temperature indicator
TEMP_ALERTn_1V8 1 Intel® Stratix® 10 temperature alert indicator
Global Clocks
CLK_50M_S10 1 50 MHz Global clock input
CLK_TOP_PLL_125M_p/n 2 125 MHz differential core clock for top
CLKIN_SMA_2L_p/n 2 Global Clock input from SMA
CLKOUT_SMA_2L_p/n 2 Dedicated Clock output to SMA
USB_FPGA_CLK 1 USB FPGA Clock
CLK_BOT_PLL_100M_p/n 2 100 MHz differential core clock for bottom
Transceiver Clocks
CLK_9C_OSC_156M_p/n 2 Differential REFCLK to xcvr bank 9C
CLK_9B_OSC_156M_p/n 2 Differential REFCLK to xcvr bank 9B
CLK_9A_OSC_156M_p/n 2 Differential REFCLK to xcvr bank 9A
CLK_8C_OSC_156M_p/n 2 Differential REFCLK to xcvr bank 8C
CLK_8B_OSC_156M_p/n 2 Differential REFCLK to xcvr bank 8B
CLK_9C_PLL_322M_p/n 2 Differential REFCLK to xcvr bank 9C
CLK_9B_PLL_322M_p/n 2 Differential REFCLK to xcvr bank 9B
CLK_9A_PLL_176M_p/n 2 Differential REFCLK to xcvr bank 9A
CLK_8C_PLL _176M_p/n 2 Differential REFCLK to xcvr bank 8C
CLK_8B_PLL _307M_p/n 2 Differential REFCLK to xcvr bank 8B
CLK_1E_PLL_307M_p/n 2 Differential REFCLK to xcvr bank 1E
CLKIN_SMA_1D_p/n 2 Differential REFCLK to xcvr bank 1D
CLKIN_SMA_8B_p/n 2 Differential REFCLK to xcvr bank 8B
CLKIN_SMA_8C_p/n 2 Differential REFCLK to xcvr bank 8C
CLKIN_SMA_9A_p/n 2 Differential REFCLK to xcvr bank 9A
CLKIN_SMA_9B_p/n 2 Differential REFCLK to xcvr bank 9B
CLKIN_SMA_9C_p/n 2 Differential REFCLK to xcvr bank 9C
FAGBTCLKM2CP/N[5:0] 12 Differential REFCLK to xcvr bank 8B
Note: SmartVID graded devices require the use of a configurable voltage regulator or system controller to receive the device's settings through the Power Management Bus (PMBus™) or Pulse-Width Modulation (PWM) interface for proper performance.
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