Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

ID 683591
Date 9/27/2019
Document Table of Contents

4.4.2. Configuring the FPGA through Flash Memory

The figure below shows a detailed schematic block diagram for the MAX® V + Flash AvSTx16 mode configuration implementation.
Note: Typical JTAG clock frequency for CFI Flash programming via PFL II core is 16 MHz. You may try it with a lower frequency such as 6 MHz if it fails with 16 MHz.
Figure 5. MAX V Configuration Block Diagram

The PGMSEL dipswitch (S5) is provided to select between POF files (FACTORY and USER) stored on the Flash.

The Parallel Flash Loader II (PFL II) Megafunction is used to implement the AvSTx16 configuration in the MAX® V CPLD. The PFL II Megafunction reads data from the flash and converts it to AvST format. This data is written into the Intel® Stratix® 10 TX FPGA device through dedicated AvST CLK and FPGA Config Data [15:0] pins at corresponding clock rate, such as 25 MHz, 50 MHz and 100 MHz.

Implementation will be done using an MAX® V 5M2210ZF256FBGA CPLD acting as the AvST download controller and two 1G Flash devices.

If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX® V device shall configure the Intel® Stratix® 10 TX FPGA in the AvST x16 mode with either the FACTORY POF or an USER DEFINED POF depnding on the FACTORY_LOAD setting.

The MSEL[2:0] pins indicate which configuration scheme is chosen. The manufacturing default condition is [001] for Fast AS x4 scheme.

For different configuration modes, MSEL [2:0] signals must be set acccording to the table below:
Table 6.  Support Configuration Modes for Stratix 10 TX Transceiver Signal Integrity
Configuration Scheme MSEL [2:0]
Avalon-ST (x16) 101
AS (Normal mode) 011
AS (Fast) 001
JTAG only 111
Not supported Other Settings