Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 11/21/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II

Embedded Intel® FPGA Download Cable II is the default method for configuring the Stratix® 10 TX FPGA using the Quartus® Prime Programmer in the JTAG mode with the supplied USB cable.

Figure 4. Embedded Intel® FPGA Download Cable II

The embedded Intel® FPGA Download Cable II for USB-based configuration of the Stratix® 10 TX FPGA device is implemented using a Type-B USB connector, a CY7C68013A USB2 PHY device, and an MAX® 10 10M04SCU169 FPGA. This will allow configuration of the Stratix® 10 TX FPGA device using a USB cable directly connected to a computer running Quartus® Prime software without requiring the external Intel® FPGA Download Cable dongle.

This design will convert USB data to interface with the Stratix® 10 TX FPGA's dedicated JTAG port. Four LEDs are provided to indicate embedded Intel® FPGA Download Cable II activity. The embedded Intel® FPGA Download Cable II is automatically disabled when an external Intel® FPGA Download Cable dongle is connected to the JTAG header.

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