Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.5. Status and Setup Elements

The development board includes board-specific status LEDs and switches for enabling and configuring various features on the board. This section describes these status elements.

Table 7.  Board Specific LEDs
Board Reference Signal Name Description
D23 –-- Green LED. Power 3.3 V present
D24 –-- Green LED. Power 3.3 V PRE present
D25 –-- Green LED. Power 12 V present
D5 PWR_ERR_LED Amber LED. System Power error indicator
D1 JTAG_RX Green LED. JTAG receiver activity indicator
D2 JTAG_TX Green LED. JTAG transmitter activity indicator
D3 SC_RX Green LED. System console receiver activity indicator
D4 SC_TX Green LED. System console transmitter activity indicator
D7 ENET_LED_TX

Green LED. Blinks to indicate Ethernet PHY transmit activity
D8 ENET_LED_RX

Green LED. Blinks to indicate Ethernet PHY receive activity.
D9 ENET_LED_LINK1000

Green LED. Illuminates to indicate Ethernet linked at 1000 Mbps connection speed

D10 ENET_LED_LINK100

Green LED. Illuminates to indicate Ethernet linked at 100 Mbps connection speed

D11 ENET_LED_LINK10

Green LED. Illuminates to indicate Ethernet linked at 10 Mbps connection speed

D6 OVERTEMP Amber LED. Intel® Stratix® 10 FPGA over temperature indicator
This development board includes several different kinds of setup elements. This section describes the following setup elements:
  • JTAG Chain Device Removal Switch
  • Program Select Pushbutton
  • MAX® V Reset Pushbutton
  • CPU Reset Pushbutton

JTAG Chain Device Removal Switch

The JTAG chain connects the Intel® Stratix® 10 TX FPGA, the MAX V CPLD, FMC in a chain, with the option to selectively bypass each JTAG node by four dip switch setting.

Program Select Pushbutton

If AvST configuration mode is selected, after a POWER-ON or RESET (reconfiguration) event, the MAX® V configures the Intel® Stratix® 10 TX FPGA if configuration mode is AvST mode with either the FACTORY POF or a USERDEFINED POF depending on FACTORY_LOAD setting. The setting of the PGMSEL bit is selected by the PGMSEL pushbutton. Pressing this pushbutton and observing the program LEDs (FACTORY or USER) dictates the program selection. Then, the PGM_CONFIG pushbutton must be pressed to load the program.

MAX® V Reset Pushbutton

This pushbutton is the development board's Master Reset. This pushbuttton is connected to the MAX® V CPLD (MAX_RESETn pin) that is used for AvST configuration. When this button is pressed, the MAX® V CPLD initiates a reloading of the stored image from flash memory using AvST configuration mode. The image that is reloaded depends on the PGMSEL setting.

CPU Reset Pushbutton

This pushbutton is the Nios® II CPU Reset. This button is connected to a Intel® Stratix® 10 TX FPGA global signal input pin and can be used by Nios® II implementations as a dedicated CPU Reset button. This button is also connected to the MAX® V CPLD so that the FPGA device can be reset right after its configuration with AvST mode.

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