Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

ID 683591
Date 9/27/2019
Document Table of Contents

4.3. MAX® V CPLD

The Intel® Stratix® 10 TX transceiver signal integrity development kit consists of a MAX® V CPLD (5M2210Z-F256), 256-pin FineLine BGA package. MAX® V CPLD devices provide programmable solutions for applications such as FPGA reconfiguration from flash memory, I2C chain to manage power consumption, core temperature, fan speed, clock frequency. MAX® V devices feature on-chip flash storage, internal oscillator and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX® V CPLDs can help you meet your low power design requirements.

The following list summarizes the features of MAX® V CPLD devices:
  • 2210 Logic Elements (LEs)
  • 8192 bits of User Flash Memory
  • 4 global clocks
  • 1 internal oscillator
  • 271 maximum user I/O pins
  • Low-cost, low power and non-volatile CPLD architecture
  • Fast propagation delays and clock-to-output times
  • Single 1.8V external supply for device core
  • Bus-friendly architecture including programmable slew rate, drive strength, bushold and programmable pull-up resistors
Table 5.   MAX® V I/O Summary
Signal Name Description
FA_A[27:1] Flash Address Bus
FM_D[15:0] Flash Data Bus
FLASH_RESETn Flash reset
FLASH_CEn[1:0] Flash chip enable
FLASH_OEn Flash output enable
FLASH_WEn Flash write enable
FLASH_WPn Flash write protection
FLASH_RDYBSYn Flash chip ready/busy
FLASH_BYTEn Flash byte enable
FPGA_CONFIG_D[15:0] FPGA AvST Configuration Data Bus
FPGA_INIT_DONE FPGA initialization complete
FPGA_CONF_DONE FPGA configuration complete
FPGA_nCONFIG FPGA configuration control pin to reset FPGA
FPGA_SEU_ERR FPGA configuration SEU error
FPGA_CvP_DONE FPGA CvP configuration done
FPGA_PR_REQUEST FPGA partial reconfiguration request
FPGA_PR_DONE FPGA partial reconfiguration done
FPGA_PR_ERROR FPGA partial reconfiguration error
FPGA_MSEL[2:0] FPGA configuration mode setting bits
FPGA_AVST_CLK FPGA AvST Configuration clock
FPGA_AVST_VALID FPGA AvST Configuration data valid
FPGA_AVST_READY FPGA AvST Ready to receive data
I2C_1V8_SCL MAX V I2C bus
I2C_1V8_SDA MAX V I2C bus
SI5341_ENn SI5341 1 enable
SI5341_INTn SI5341 1 interrupt indicators
SI5341_RSTn SI5341 1 reset
SI5341_LOLn SI5341 1 loss of lock indicators
SI547_FS[1:0] SI547 frequency selection bits when Si549 is replaced with Si547
PCIe_PERSTn_1V8 1.8V PCIe reset signal
PCIe_PERSTn_3V3 3.3V PCIe reset signal
PCIe_WAKEn_3V3 3.3V PCIe wake signal
FACLKDIR FMC+ bi-directional clock direction selection bit
PMBUS_ALERTn VCC regulator alert
I2C_PWR_ALERTn Other regulators alert
VCC_ALERTn 1.8V VCC regulator alert
EN_MASTER[2:0] Enable specific I2C buffer
OVERTEMPn_1V8 FPGA over temperature input 1.8V
TEMP_ALERTn FPGA temperature alert output
OVERTEMPn FPGA over temperature output
TEMP_ALERTn_1V8 FPGA temperature alert input 1.8V
USB_CFG[14:0] Bus between USB MAX 10 and MAX® V
USB_SYSMAX_CLK Clock from USB PHY chip
MAX_OSC_CLK_1 25M/100M/125MHz clock input
FACTORY_LOAD Factory image for configuration
MAX5_SWITCH[2:0] System MAX® V user dipswitch
PGM_SEL Flash memory PGM select pushbutton
PGM_CONFIG Flash memory PGM configuration pushbutton
MAX_RESETn System MAX® V reset pushbutton
CPU_RESETn CPU reset pushbutton
PGM_LED[2:0] Flash image PGM select indicators
MAXV_ERROR Intel® Stratix® 10 configuration error indicator LED
MAXV_LOAD Intel® Stratix® 10 configuration active indicator LED
MAXV_CONF_DONE Intel® Stratix® 10 configuration done indicator LED
USER_IO[9:0] User general I/Os
CLK_50M_SYSMAX 50 MHz Clock input
OPT_FAN_RPM Optical interface fan speed control
FAN_RPM FPGA fan speed control
Figure 3. I2C Diagram