Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

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ID 683591
Date 9/27/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Kit
2. Getting Started x
2.1. About the Intel® Quartus® Prime Software 2.2. Development Kit Package 2.3. Installing the Intel® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Setting up the Development Kit 3.2. Factory Default Switch and Jumper Settings
4. Development Kit Components x
4.1. Development Kit Overview 4.2. Intel® Stratix® 10 TX FPGA 4.3. MAX® V CPLD 4.4. FPGA Configuration 4.5. Status and Setup Elements 4.6. User Input-Output Components 4.7. Clocks 4.8. Transceiver Channels 4.9. Communication Ports 4.10. Flash Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Configuring the FPGA over Embedded Intel® FPGA Download Cable II 4.4.2. Configuring the FPGA through Flash Memory 4.4.3. Configuring the FPGA over External Intel® FPGA Download Cable
4.7. Clocks x
4.7.1. Transceiver Dedicated Clocks 4.7.2. General-Purpose Clocks 4.7.3. Embedded Intel® FPGA Download Cable II Clock
4.10. Flash Memory x
4.10.1. Parallel NOR Flash Memory 4.10.2. EPCQL Flash Memory
4.11. System Power x
4.11.1. Power Guidelines 4.11.2. Power Supply 4.11.3. Power Management 4.11.4. Power Distribution System 4.11.5. Thermal Limitations and Protection Guidelines
5. Board Test System x
5.1. Preparing the Development Kit 5.2. Running the Board Test System 5.3. Using the Board Test System 5.4. Simple Socket Server
5.3. Using the Board Test System x
5.3.1. The Configure Menu 5.3.2. The System Info Tab 5.3.3. The GPIO Tab 5.3.4. The EPCQ Tab 5.3.5. The FMC+ Tab 5.3.6. The PAM4 Tab 5.3.7. The MXP Tab 5.3.8. The QSFPDD1x2 Tab 5.3.9. The QSFPDD2x1 Tab 5.3.10. Power Monitor 5.3.11. Clock Controller
A. Additional Information x
A.1. Add SmartVID settings in QSF file A.2. Safety and Regulatory Information A.3. Compliance and Conformity Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.11.2. Power Supply

Power supply for this development kit is provided through an external laptop style DC power brick connected to a 6-pin ATX power connector. The input voltage is in the range of 12V +/- 5%. This DC voltage is then stepped down to the various power rails used by the components on the development kit.

Note: The power rails on the development board have the option to be supplied from an external source through a banana jack or power terminal connectors by first disabling corresponding power regulator using SW2/SW3 DIP Switch.
Table 20.  Power Per Device
Device Voltage Name Voltage Description

Intel® Stratix® 10 (1ST280EYF2912)

S10_VCC 0.85/VID Core and periphery power
S10_VCCH_E 1.1 E-tile XCVR power
S10_VCCR 1.12/1.03 H-tile XCVR RX path
S10_VCCT 1.12/1.03 H-tile XCVR TX path
S10_VCCERAM 0.9 Memory and PLL digital power
S10_VCCERT 0.9 E-tile XCVR power
S10_1V8 1.8 IO voltage, I/O pre-drivers
S10_2V4 2.4 VCCFUSEWR power
S10_2V5 2.5 E-tile XCVR power

USB Intel® MAX® 10

(10M04SCU169)

3.3V_PRE

1.8V_PRE

3.3

1.8

Core, PLL and VCCIO

VCCIO for Stratix 10 Interface

PWR Intel® MAX® 10

(10M16SAU169)

 3.3V_STBY 3.3 Intel power management chip
MAX V (EPM2210F256)

S10_1V8

IO_3V3

1.8

3.3

 System controller
Flash S10_1V8 1.8 CFI Flash
USB PHY(CY7C68103) 3.3V_PRE 3.3 USB PHY
Ethernet PHY(88E1111) IO_2V5 2.5 Ethernet PHY
Clock Buffer (SL18860DC) 1.8V_PRE 1.8 Core clock buffer
Clock Buffer (Si53311) IO_2V5 2.5 Transceiver Reference Clock Buffers

Programmable PLL

(Si5341)

S10_1V8

IO_2V5

IO_3V3

1.8

2.5

3.3

 Transceiver Reference clock and core clock
Oscillator (Si549) IO_3V3 3.3 Oscillator

Temperature monitor

(MAX6581)

 IO_3V3 3.3 Temperature monitor chip
QSFPDD Modules IO_3V3 3.3 QSFP28 Modules
FMC

S10_1V8

IO_3V3

IO_12V

1.8

3.3

12

 FMC+ interface
Level Two Title