Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide

ID 683591
Date 9/27/2019
Document Table of Contents

4.7.2. General-Purpose Clocks

In addition to transceiver dedicated clocks, five other clock sources are provided to the FPGA Global CLK inputs for general FPGA design as shown in the figure below.

The usage of these clocks is as follows:
  • 50 MHz oscillator through an SL18860 buffer for Nios® II applications. USB_FPGA_CLK drives from on-board Intel® FPGA Download Cable II circuit.
  • External differential clock source from SMA connectors. Dedicated differential output clock to SMA connectors.
  • Three clock outputs are provided from two Si5341 PLLs:
    • CLK_BOT_PLL_100M_P/N: 100 MHz LVDS Standard
    • CLK_TOP_PLL_125M_P/N: 125 MHz LVDS Standard
    • FPGA_OSC_CLK_1: 125 MHz 1.8V CMOS Standard
  • Clocks from FMC+ daughter card
Figure 8. FPGA Clocks