Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
3.1.3. RTL Simulation Setup Scripts
Platform Designer generates scripts for several simulators that you can use to complete the simulation process, as listed in the following table.
Simulator | Script Name | Directory |
---|---|---|
Questa*-Altera® FPGA Edition (Questa_fe) | msim_setup.tcl | <project directory>/<Platform Designer design name>/sim/mentor |
Cadence® Xcelium* | xcelium_setup.sh | <project directory>/<Platform Designer design name>/sim/xcelium |
Synopsys* VCS* MX | vcsmx_setup.sh | <project directory>/<Platform Designer design name>/sim/synopsys/vcsmx |
Aldec® Riviera-PRO* | rivierapro_setup.tcl | <project directory>/<Platform Designer design name>/sim/aldec |
Note: The (1) Questa*-Altera® FPGA Edition is licensed together with the Quartus® Prime Pro Edition software. You need to purchase a separate license to use the (2) Siemens* EDA QuestaSIM* , (3) Cadence® NCSim, (4) Synopsys* VCS* , and (5) Synopsys* VCS* MX simulators. For information about the purchase of licenses, access the respective official websites.
The following sections show the detailed steps on creating the test scripts for the supported simulators.