Agilex™ 7 Hard Processor System Component Reference Manual
ID
683581
Date
10/08/2025
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the Agilex™ 7 HPS Component Revision History
2.2.1.3. Enable Debug APB Interface
The debug Advanced Peripheral Bus (APB)* interface allows debug components in the FPGA fabric to access debug components in the HPS.
For more information about the Debug APB interface, refer to the CoreSight* Debug and Trace chapter in the Agilex™ 7 Hard Processor System Technical Reference Manual.
Turning on this option enables the following interfaces and signals:
Interface Name | Interface Type | Signals |
---|---|---|
h2f_debug_apb_clock | Clock Input | h2f_dbg_apb_clk |
h2f_debug_apb_reset | Reset Output | h2f_dbg_apb_rst_n |
h2f_debug_apb | APB Master | h2f_dbg_apb_PADDR[14..0] h2f_dbg_apb_PADDR31 h2f_dbg_apb_PENABLE h2f_dbg_apb_PRDATA[31..0] h2f_dbg_apb_PREADY h2f_dbg_apb_PSEL h2f_dbg_apb_PSLVERB h2f_dbg_apb_PWDATA[31..0] h2f_dbg_apb_PWRITE |
h2f_debug_apb_sideband | Conduit | h2f_debug_apb_PCLKEN h2f_debug_apb_DBG_APB_DISABLE |
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